Solution
Failure Prediction & Diagnostics
When a card fails today, nobody can say which logic caused it. Fluid Silicon measures every element, so a fault has an address, a history and a forecast.
Measured impact
On production shells, at realistic utilization.
*Fluid Silicon measurements. Varies with variation pattern, workload, vendor and device age.
Applications
Four applications, one measurement.
Degradation Prediction
A forecast per card and per element, from measured history.
Learn moreError Attribution
An error tied to the element that caused it, with the measurements to prove it.
Learn moreOutlier Detection
The cards and elements far from the rest of the fleet, before they fail.
Learn moreEvidence for Root Cause
Per-element history for your reliability engineers and your vendors.
Learn moreDegradation Prediction
Which card fails next, and when.
- Every element measured about once a second for the life of the card.
- A per-card aging curve fitted to its temperature history.
- A time-to-threshold that feeds replacement and capacity planning.
- Cards aging faster than their neighbours flagged early.
Prediction, not a schedule
Replacing boards on a fixed schedule retires healthy cards and misses failing ones. A forecast per card replaces the schedule.
Error Attribution
A fault with an address.
- Per-element slack history around the time of an error.
- The weakest element on the card, and how long it has been weakening.
- Evidence that separates a timing fault from a software or thermal event.
- Reports your reliability team can attach to a ticket.
Before the error travels
An error in one card can take capacity offline or propagate downstream. Attribution shortens the path from symptom to cause.
- Last sweep
- 2 min ago, 1.0 s
- Aging model
- Power-law fit to this card's temperature history
- Recommended action
- Schedule a repair window
- Approval
- Waiting for your change process
Outlier Detection
The tails of the fleet.
- Each card's weakest element compared across the fleet.
- Systematic and random variation separated from aging.
- Cards far below the family median surfaced first.
- The same comparison on AMD and Altera parts.
Variation at scale
At 16, 14 and 7 nm, random variation alone exceeds 20%, on top of systematic variation across the die. Measuring more chips finds more tails.
Evidence for Root Cause
Data your vendors can act on.
- Per-element measurements from the day a card entered service.
- Temperature and operating-point history alongside timing.
- Exit characterization when a card leaves service.
- One vendor-neutral format for your team and your suppliers.
Feedback to the silicon vendor
A card returned with a measured history is a different conversation from a card returned with a symptom.
Industries
Where it applies.
Resources
BlogAging is measurable, in the field
Temperature sets the aging rate. The same board reaches its threshold years apart in a cool rack and a hot enclosure, and now that can be measured.
ReadThe FPGA margin problem
Why timing models carry 30–54% margin for the worst chip in the population, why that was the right call, and what per-chip measurement changes.
ReadRead-only first: how an evaluation runs
Evaluate, observe, optimize, repair: four opt-in steps, and what each needs from your team.
ReadFAQ
Common questions.
Sensor architecture, deployment mechanics and calibration methods are shared with evaluation partners under NDA.
What kinds of failure does this predict?
Timing failures from variation and wear-out: logic that has slowed past its margin. It does not predict mechanical, power-supply or radiation events; it complements the measures you have for those.
How is an error attributed?
Every logic element has a measured slack history, so an error is checked against the elements that were weakest at the time. The result is evidence, not inference.
Can it tell aging from a bad batch?
Yes. Aging shows as a trend in a card's own history; a bad batch shows as an outlier at incoming characterization, before the card ages at all.
Does monitoring affect our design's timing?
The health layer adds under 2% delay and occupies under 1% of LUTs on a production shell. It does not interfere with the design's computation.
How often is each card measured?
A full sweep of every logic element takes about a second and runs while the design computes. The interval between sweeps is yours to set.
Which devices are supported?
AMD 7-series, UltraScale and UltraScale+ today, with select Altera Agilex 7 devices; more families in development. See device support.
Measure a device at speed, live.
A 30-minute session: in-system slack measurements on a supported AMD or Altera device, and what an evaluation on your boards involves.