Blog and resources
Posts on margins, aging, fleets and how an evaluation runs.
Posts
The FPGA margin problem
Why timing models carry 30–54% margin for the worst chip in the population, why that was the right call, and what per-chip measurement changes.
ReadAging is measurable, in the field
Temperature sets the aging rate. The same board reaches its threshold years apart in a cool rack and a hot enclosure, and now that can be measured.
ReadFive board generations, one health metric
What mixed-vendor, multi-generation fleets need from telemetry: one number that means one thing on every part.
ReadWhat a point of card power is worth
A worked example for 10,000 cards: the arithmetic behind adaptive voltage scaling at fleet scale.
ReadRead-only first: how an evaluation runs
Evaluate, observe, optimize, repair: four opt-in steps, and what each needs from your team.
ReadFollow along
New posts, on LinkedIn.
New explainers and company updates are posted on LinkedIn. Prefer email? Write to us.
Measure a device at speed, live.
A 30-minute session: in-system slack measurements on a supported AMD or Altera device, and what an evaluation on your boards involves.